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Module Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch23_main.DtpTxSerAdapt_sram_axi_s0_T.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch15_main.DtpTxSerAdapt_fpga_ahb_s0_T.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch15Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch4Resp001_main.DtpRxSerAdapt_Switch15Resp.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch7.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.76 75.00 72.73 18.75 68.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.80 75.00 75.00 18.91 70.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
18.91 18.91 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 75.00 100.00 25.00 100.00
uco 35.00 35.00
ur 25.00 25.00
ut89 18.06 18.06


Module Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch4.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
54.62 75.00 72.73 2.18 68.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
55.51 75.00 75.00 1.76 70.27


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
4.31 4.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 66.67 100.00 0.00 100.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch20_main.DtpTxSerAdapt_sram_axi_s3_T.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch14_main.DtpTxSerAdapt_sram_axi_s2_T.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch13_main.DtpTxSerAdapt_sram_axi_s1_T.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.81 75.00 45.45 0.51 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.82 75.00 45.83 0.41 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.31 1.31 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.83 75.00 45.45 0.58 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.84 75.00 45.83 0.47 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.50 1.50 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00


Module Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.45 0.65 54.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
43.85 75.00 45.83 0.53 54.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
1.69 1.69 Iu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ubm 33.33 50.00 0.00 50.00
uco 0.00 0.00
ur 0.00 0.00
ut89 0.00 0.00

Go back
Module Instances:
config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch23_main.DtpTxSerAdapt_sram_axi_s0_T.Iu.A0
config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch15_main.DtpTxSerAdapt_fpga_ahb_s0_T.Iu.A0
config_ss_tb.DUT.flexnoc.Switch15Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch4Resp001_main.DtpRxSerAdapt_Switch15Resp.Iu.A0
config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch7.Iu.A0
config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch4.Iu.A0
config_ss_tb.DUT.flexnoc.Switch20_main.DtpTxSerAdapt_sram_axi_s3_T.Iu.A0
config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
config_ss_tb.DUT.flexnoc.Switch14_main.DtpTxSerAdapt_sram_axi_s2_T.Iu.A0
config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
config_ss_tb.DUT.flexnoc.Switch13_main.DtpTxSerAdapt_sram_axi_s1_T.Iu.A0
config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch16Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23_main.DtpTxSerAdapt_sram_axi_s0_T.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23_main.DtpTxSerAdapt_sram_axi_s0_T.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23_main.DtpTxSerAdapt_sram_axi_s0_T.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23_main.DtpTxSerAdapt_sram_axi_s0_T.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch23Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15_main.DtpTxSerAdapt_fpga_ahb_s0_T.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15_main.DtpTxSerAdapt_fpga_ahb_s0_T.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15_main.DtpTxSerAdapt_fpga_ahb_s0_T.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15_main.DtpTxSerAdapt_fpga_ahb_s0_T.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch15Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch4Resp001_main.DtpRxSerAdapt_Switch15Resp.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch4Resp001_main.DtpRxSerAdapt_Switch15Resp.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch4Resp001_main.DtpRxSerAdapt_Switch15Resp.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch4Resp001_main.DtpRxSerAdapt_Switch15Resp.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch7.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch7.Iu.A0
TotalCoveredPercent
Conditions221672.73
Logical221672.73
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch7.Iu.A0
TotalCoveredPercent
Totals 62 5 8.06
Total Bits 1376 258 18.75
Total Bits 0->1 688 250 36.34
Total Bits 1->0 688 8 1.16

Ports 19 4 21.05
Port Bits 534 101 18.91
Port Bits 0->1 267 96 35.96
Port Bits 1->0 267 5 1.87

Signals 43 1 2.33
Signal Bits 842 157 18.65
Signal Bits 0->1 421 154 36.58
Signal Bits 1->0 421 3 0.71

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[0] No No Yes INPUT
Rx_Data[2:1] No No No INPUT
Rx_Data[5:3] No No Yes INPUT
Rx_Data[6] No No No INPUT
Rx_Data[8:7] No No Yes INPUT
Rx_Data[19:9] No No No INPUT
Rx_Data[20] No No Yes INPUT
Rx_Data[21] No No No INPUT
Rx_Data[22] No No Yes INPUT
Rx_Data[23] No No No INPUT
Rx_Data[33:24] No No Yes INPUT
Rx_Data[34] No No No INPUT
Rx_Data[35] No No Yes INPUT
Rx_Data[46:36] No No No INPUT
Rx_Data[47] No No Yes INPUT
Rx_Data[48] No No No INPUT
Rx_Data[49] No No Yes INPUT
Rx_Data[50] No No No INPUT
Rx_Data[51] No No Yes INPUT
Rx_Data[52] No No No INPUT
Rx_Data[54:53] No No Yes INPUT
Rx_Data[55] No No No INPUT
Rx_Data[56] No No Yes INPUT
Rx_Data[61:57] No No No INPUT
Rx_Data[62] No No Yes INPUT
Rx_Data[76:63] No No No INPUT
Rx_Data[78:77] No No Yes INPUT
Rx_Data[80:79] No No No INPUT
Rx_Data[81] No No Yes INPUT
Rx_Data[84:82] No No No INPUT
Rx_Data[91:85] No No Yes INPUT
Rx_Data[92] No No No INPUT
Rx_Data[94:93] No No Yes INPUT
Rx_Data[95] No No No INPUT
Rx_Data[98:96] No No Yes INPUT
Rx_Data[117:99] No No No INPUT
Rx_Data[118] No No Yes INPUT
Rx_Data[122:119] No No No INPUT
Rx_Data[123] No No Yes INPUT
Rx_Data[129:124] No No No INPUT
Rx_Data[132:130] No No Yes INPUT
Rx_Data[136:133] No No No INPUT
Rx_Data[137] No No Yes INPUT
Rx_Data[142:138] No No No INPUT
Rx_Head No No Yes INPUT
Rx_Rdy Yes Yes Yes OUTPUT
Rx_Tail No No Yes INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[0] No No Yes OUTPUT
Tx_Data[2:1] No No No OUTPUT
Tx_Data[5:3] No No Yes OUTPUT
Tx_Data[6] No No No OUTPUT
Tx_Data[8:7] No No Yes OUTPUT
Tx_Data[19:9] No No No OUTPUT
Tx_Data[20] No No Yes OUTPUT
Tx_Data[21] No No No OUTPUT
Tx_Data[22] No No Yes OUTPUT
Tx_Data[23] No No No OUTPUT
Tx_Data[33:24] No No Yes OUTPUT
Tx_Data[34] No No No OUTPUT
Tx_Data[35] No No Yes OUTPUT
Tx_Data[40:36] No No No OUTPUT
Tx_Data[42:41] No No Yes OUTPUT
Tx_Data[44:43] No No No OUTPUT
Tx_Data[45] No No Yes OUTPUT
Tx_Data[48:46] No No No OUTPUT
Tx_Data[55:49] No No Yes OUTPUT
Tx_Data[56] No No No OUTPUT
Tx_Data[58:57] No No Yes OUTPUT
Tx_Data[59] No No No OUTPUT
Tx_Data[62:60] No No Yes OUTPUT
Tx_Data[81:63] No No No OUTPUT
Tx_Data[82] No No Yes OUTPUT
Tx_Data[86:83] No No No OUTPUT
Tx_Data[87] No No Yes OUTPUT
Tx_Data[93:88] No No No OUTPUT
Tx_Data[96:94] No No Yes OUTPUT
Tx_Data[100:97] No No No OUTPUT
Tx_Data[101] No No Yes OUTPUT
Tx_Data[106:102] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No Yes OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[0] No No Yes
u_255f[1] No No No
u_2e4d[0] No No Yes
u_2e4d[1] No No No
u_3bd7[1:0] No No No
u_3bd7[2] No No Yes
u_3bd7[6:3] No No No
u_4d3d[3:0] No No No
u_56 No Yes No
u_5925[0] No No Yes
u_5925[2:1] No No No
u_5925[3] No No Yes
u_5925[5:4] No No No
u_5925[6] No No Yes
u_5925[10:7] No No No
u_5925[11] No No Yes
u_5925[17:12] No No No
u_5925[19:18] No No Yes
u_5925[20] No No No
u_5925[22:21] No No Yes
u_5925[23] No No No
u_5925[24] No No Yes
u_5925[26:25] No No No
u_5925[27] No No Yes
u_5925[31:28] No No No
u_5925[32] No No Yes
u_5925[33] No No No
u_5925[35:34] No No Yes
u_5925[36] No No No
u_5925[37] No No Yes
u_5925[39:38] No No No
u_5925[40] No No Yes
u_5925[42:41] No No No
u_5925[43] No No Yes
u_5925[49:44] No No No
u_5925[51:50] No No Yes
u_5925[52] No No No
u_5925[53] No No Yes
u_5925[55:54] No No No
u_5925[56] No No Yes
u_5925[57] No No No
u_5925[58] No No Yes
u_5925[63:59] No No No
u_5925[64] No No Yes
u_5925[65] No No No
u_5925[67:66] No No Yes
u_5925[68] No No No
u_5925[70:69] No No Yes
u_5925[71] No No No
u_686c[1:0] No No Yes
u_760c[1:0] No No No
u_760c[2] No No Yes
u_760c[6:3] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[1:0] No No Yes
u_a1a5[2] No No No
u_b4b7[6:0] No No Yes
u_b4b7[7] No No No
u_b4b7[9:8] No No Yes
u_b4b7[10] No No No
u_b4b7[13:11] No No Yes
u_b4b7[30:14] No No No
Addr[2:0] No No Yes
Be[0] No No Yes
Be[1] No No No
Be[3:2] No No Yes
Be[4] No No No
Be[6:5] No No Yes
Be[7] No No No
BeGrp[0] No No Yes
BeGrp[1] No No No
DSel No No Yes
DSelReg No No No
End No No No
HasData No Yes No
Head No No No
Info[1:0] No No No
Info[5:2] No No Yes
Info[7:6] No No No
Info1[1:0] No No No
Info1[5:2] No No Yes
Info1[7:6] No No No
Info1Reg[7:0] No No No
Last No No Yes
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[1:0] No No No
Len1[2] No No Yes
Len1A[1:0] No No No
Len1A[2] No No Yes
New No No No
Next Yes Yes Yes
Restart No No No
RxHdr[2:0] No No No
RxHdr[4:3] No No Yes
RxHdr[6:5] No No No
RxHdr[7] No No Yes
RxHdr[10:8] No No No
RxHdr[17:11] No No Yes
RxHdr[18] No No No
RxHdr[20:19] No No Yes
RxHdr[21] No No No
RxHdr[24:22] No No Yes
RxHdr[43:25] No No No
RxHdr[44] No No Yes
RxHdr[48:45] No No No
RxHdr[49] No No Yes
RxHdr[55:50] No No No
RxHdr[58:56] No No Yes
RxHdr[62:59] No No No
RxHdr[63] No No Yes
RxHdr[68:64] No No No
RxOpc[3:0] No No No
RxPld[0] No No Yes
RxPld[2:1] No No No
RxPld[5:3] No No Yes
RxPld[6] No No No
RxPld[8:7] No No Yes
RxPld[19:9] No No No
RxPld[20] No No Yes
RxPld[21] No No No
RxPld[22] No No Yes
RxPld[23] No No No
RxPld[33:24] No No Yes
RxPld[34] No No No
RxPld[35] No No Yes
RxPld[46:36] No No No
RxPld[47] No No Yes
RxPld[48] No No No
RxPld[49] No No Yes
RxPld[50] No No No
RxPld[51] No No Yes
RxPld[52] No No No
RxPld[54:53] No No Yes
RxPld[55] No No No
RxPld[56] No No Yes
RxPld[61:57] No No No
RxPld[62] No No Yes
RxPld[73:63] No No No
RxVld No No No
TxData[0] No No Yes
TxData[2:1] No No No
TxData[5:3] No No Yes
TxData[6] No No No
TxData[8:7] No No Yes
TxData[19:9] No No No
TxData[20] No No Yes
TxData[21] No No No
TxData[22] No No Yes
TxData[23] No No No
TxData[33:24] No No Yes
TxData[34] No No No
TxData[35] No No Yes
TxPld[0] No No Yes
TxPld[2:1] No No No
TxPld[5:3] No No Yes
TxPld[6] No No No
TxPld[8:7] No No Yes
TxPld[19:9] No No No
TxPld[20] No No Yes
TxPld[21] No No No
TxPld[22] No No Yes
TxPld[23] No No No
TxPld[33:24] No No Yes
TxPld[34] No No No
TxPld[35] No No Yes
TxPld[37:36] No No No
TxTail No No Yes
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch7.Iu.A0
Line No.TotalCoveredPercent
Branches 35 24 68.57
TERNARY 27351 2 2 100.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 2 66.67
TERNARY 27378 2 2 100.00
TERNARY 27408 2 2 100.00
TERNARY 27411 2 2 100.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch4.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch4.Iu.A0
TotalCoveredPercent
Conditions221672.73
Logical221672.73
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch4.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 30 2.18
Total Bits 0->1 688 25 3.63
Total Bits 1->0 688 5 0.73

Ports 19 3 15.79
Port Bits 534 23 4.31
Port Bits 0->1 267 18 6.74
Port Bits 1->0 267 5 1.87

Signals 43 0 0.00
Signal Bits 842 7 0.83
Signal Bits 0->1 421 7 1.66
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[130:0] No No No INPUT
Rx_Data[134:131] No No Yes INPUT
Rx_Data[135] No No No INPUT
Rx_Data[136] No No Yes INPUT
Rx_Data[137] No No No INPUT
Rx_Data[138] No No Yes INPUT
Rx_Data[142:139] No No No INPUT
Rx_Head No Yes No INPUT
Rx_Rdy No No Yes OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[94:0] No No No OUTPUT
Tx_Data[98:95] No No Yes OUTPUT
Tx_Data[99] No No No OUTPUT
Tx_Data[100] No No Yes OUTPUT
Tx_Data[101] No No No OUTPUT
Tx_Data[102] No No Yes OUTPUT
Tx_Data[106:103] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No Yes
Restart No No No
RxHdr[56:0] No No No
RxHdr[60:57] No No Yes
RxHdr[61] No No No
RxHdr[62] No No Yes
RxHdr[63] No No No
RxHdr[64] No No Yes
RxHdr[68:65] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch5_main.DtpTxSerAdapt_Switch4.Iu.A0
Line No.TotalCoveredPercent
Branches 35 24 68.57
TERNARY 27351 2 2 100.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 2 66.67
TERNARY 27378 2 2 100.00
TERNARY 27408 2 2 100.00
TERNARY 27411 2 2 100.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20_main.DtpTxSerAdapt_sram_axi_s3_T.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20_main.DtpTxSerAdapt_sram_axi_s3_T.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20_main.DtpTxSerAdapt_sram_axi_s3_T.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch20_main.DtpTxSerAdapt_sram_axi_s3_T.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14_main.DtpTxSerAdapt_sram_axi_s2_T.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14_main.DtpTxSerAdapt_sram_axi_s2_T.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14_main.DtpTxSerAdapt_sram_axi_s2_T.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14_main.DtpTxSerAdapt_sram_axi_s2_T.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch4Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch14Resp_main.DtpTxSerAdapt_Switch6Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13_main.DtpTxSerAdapt_sram_axi_s1_T.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13_main.DtpTxSerAdapt_sram_axi_s1_T.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13_main.DtpTxSerAdapt_sram_axi_s1_T.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 7 0.51
Total Bits 0->1 688 4 0.58
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 7 1.31
Port Bits 0->1 267 4 1.50
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No No INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13_main.DtpTxSerAdapt_sram_axi_s1_T.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
TotalCoveredPercent
Totals 62 2 3.23
Total Bits 1376 8 0.58
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 3 0.44

Ports 19 2 10.53
Port Bits 534 8 1.50
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 3 1.12

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy No No Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch1Resp002.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
TOTAL201575.00
ALWAYS273804375.00
ALWAYS273854375.00
ALWAYS273904375.00
ALWAYS273954375.00
ALWAYS274144375.00

27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 1/1 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 1/1 , .Sys_Pwr_Idle( ) 27383 0/1 ==> , .Sys_Pwr_WakeUp( ) MISSING_ELSE 27384 , .Tx_Data( RspTx_Data ) 27385 1/1 , .Tx_Head( RspTx_Head ) 27386 1/1 , .Tx_Rdy( RspTx_Rdy ) 27387 1/1 , .Tx_Tail( RspTx_Tail ) 27388 0/1 ==> , .Tx_Vld( RspTx_Vld ) MISSING_ELSE 27389 , .Vld( Arb_Vld ) 27390 1/1 ); 27391 1/1 assign CxtRdy = Rsp_Rdy; 27392 1/1 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 0/1 ==> .Rx_2( u_8bb4_2 ) MISSING_ELSE 27394 , .Rx_3( u_8bb4_3 ) 27395 1/1 , .Rx_4( u_8bb4_4 ) 27396 1/1 , .RxRdy( RspRdy ) 27397 1/1 , .RxVld( WrCxt ) 27398 0/1 ==> , .Sys_Clk( Sys_Clk ) MISSING_ELSE 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 1/1 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 1/1 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 1/1 .Clk( Sys_Clk ) 27417 0/1 ==> , .Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Conditions221045.45
Logical221045.45
Non-Logical00
Event00

 LINE       27351
 EXPRESSION (Rx_Head ? Info1 : Info1Reg)
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27353
 EXPRESSION (Wrap ? (((~Len1[2]) & Addr[2])) : 1'b0)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27356
 EXPRESSION (New ? (Head ? Addr[2] : Restart) : DSelReg)
             -1-
-1-Status
0Not Covered
1Covered

 LINE       27356
 SUB-EXPRESSION (Head ? Addr[2] : Restart)
                 --1-
-1-Status
0Not Covered
1Covered

 LINE       27357
 EXPRESSION (Wrap ? ((Len1[2] | Addr[2])) : 1'b1)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27362
 EXPRESSION (Wrap ? (((LastAddrA & Len1[2]) | Restart)) : LastAddrA)
             --1-
-1-Status
0Covered
1Not Covered

 LINE       27364
 EXPRESSION (Rx_Tail ? (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4))) : (DSel == End))
             ---1---
-1-Status
0Covered
1Not Covered

 LINE       27364
 SUB-EXPRESSION (Wr ? (DSel == LastAddr) : (((DSel == End) | u_93c4)))
                 -1
-1-Status
0Not Covered
1Not Covered

 LINE       27378
 EXPRESSION (HasData ? Next : Tx_Rdy)
             ---1---
-1-Status
0Not Covered
1Covered

 LINE       27408
 EXPRESSION (u_56 ? RxPld[71:36] : RxPld[35:0])
             --1-
-1-Status
0Not Covered
1Covered

 LINE       27411
 EXPRESSION (HasData ? TxTail : Rx_Tail)
             ---1---
-1-Status
0Not Covered
1Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
TotalCoveredPercent
Totals 62 3 4.84
Total Bits 1376 9 0.65
Total Bits 0->1 688 5 0.73
Total Bits 1->0 688 4 0.58

Ports 19 3 15.79
Port Bits 534 9 1.69
Port Bits 0->1 267 5 1.87
Port Bits 1->0 267 4 1.50

Signals 43 0 0.00
Signal Bits 842 0 0.00
Signal Bits 0->1 421 0 0.00
Signal Bits 1->0 421 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
Rx_Data[142:0] No No No INPUT
Rx_Head No No No INPUT
Rx_Rdy No No No OUTPUT
Rx_Tail No No No INPUT
Rx_Vld No No No INPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Tx_Data[106:0] No No No OUTPUT
Tx_Head No No No OUTPUT
Tx_Rdy Yes Yes Yes INPUT
Tx_Tail No No No OUTPUT
Tx_Vld No No No OUTPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_255f[1:0] No No No
u_2e4d[1:0] No No No
u_3bd7[6:0] No No No
u_4d3d[3:0] No No No
u_56 No No No
u_5925[71:0] No No No
u_686c[1:0] No No No
u_760c[6:0] No No No
u_8982[3:0] No No No
u_92bc[3:0] No No No
u_93c4 No No No
u_a1a5[2:0] No No No
u_b4b7[30:0] No No No
Addr[2:0] No No No
Be[7:0] No No No
BeGrp[1:0] No No No
DSel No No No
DSelReg No No No
End No No No
HasData No No No
Head No No No
Info[7:0] No No No
Info1[7:0] No No No
Info1Reg[7:0] No No No
Last No No No
LastAddr No No No
LastAddrA No No No
LastWord No No No
Len1[2:0] No No No
Len1A[2:0] No No No
New No No No
Next No No No
Restart No No No
RxHdr[68:0] No No No
RxOpc[3:0] No No No
RxPld[73:0] No No No
RxVld No No No
TxData[35:0] No No No
TxPld[37:0] No No No
TxTail No No No
WordErr No No No
Wr No No No
Wrap No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.Switch13Resp_main.DtpTxSerAdapt_Switch2Resp001.Iu.A0
Line No.TotalCoveredPercent
Branches 35 19 54.29
TERNARY 27351 2 1 50.00
TERNARY 27353 2 1 50.00
TERNARY 27356 3 1 33.33
TERNARY 27357 2 1 50.00
TERNARY 27362 2 1 50.00
TERNARY 27364 3 1 33.33
TERNARY 27378 2 1 50.00
TERNARY 27408 2 1 50.00
TERNARY 27411 2 1 50.00
IF 27380 3 2 66.67
IF 27385 3 2 66.67
IF 27390 3 2 66.67
IF 27395 3 2 66.67
IF 27414 3 2 66.67


27351 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27352 , .Clk_RstN( Sys_Clk_RstN ) 27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27353 , .Clk_Tm( Sys_Clk_Tm ) 27354 , .En( RxErr_Vld & RxErr_Rdy ) 27355 , .O( LoopPld ) 27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27356 , .Reset( RxErr_Tail ) 27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Covered
1 0 Not Covered
0 - Not Covered


27357 , .Set( LoopBack & RxErr_Head ) 27358 ); 27359 rsnoc_z_H_R_U_A_M_66382065_D108e0p0 Im( 27360 .Gnt( Arb_Gnt ) 27361 , .Rdy( Arb_Rdy ) 27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27362 , .Req( Arb_Req ) 27363 , .ReqArbIn( ) 27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Not Covered
0 Covered


27364 , .Rx_0_Data( Rsp_Data ) 27365 , .Rx_0_Head( 1'b1 ) 27366 , .Rx_0_Rdy( Rsp_Rdy ) 27367 , .Rx_0_Tail( 1'b1 ) 27368 , .Rx_0_Vld( Rsp_Vld ) 27369 , .Rx_1_Data( RspRx_Data ) 27370 , .Rx_1_Head( RspRx_Head ) 27371 , .Rx_1_Rdy( RspRx_Rdy ) 27372 , .Rx_1_Tail( RspRx_Tail ) 27373 , .Rx_1_Vld( RspRx_Vld ) 27374 , .RxLock( 2'b0 ) 27375 , .Sys_Clk( Sys_Clk ) 27376 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27377 , .Sys_Clk_En( Sys_Clk_En ) 27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> 28520 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28521 if ( ! Sys_Clk_RstN ) 28522 u_77fb <= #1.0 ( 3'b0 ); 28523 else if ( u_5717 ) 28524 u_77fb <= #1.0 ( ErrWrCxt ? ErrCxtWr_Echo : Req1_Echo ); -2- ==> ==>

Branches:
-1--2-Status
1 1 Not Covered
1 0 Not Covered
0 - Covered


27378 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27379 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27382 , .Sys_Pwr_Idle( ) 27383 , .Sys_Pwr_WakeUp( ) 27384 , .Tx_Data( RspTx_Data ) 27385 , .Tx_Head( RspTx_Head ) 27386 , .Tx_Rdy( RspTx_Rdy ) 27387 , .Tx_Tail( RspTx_Tail ) 27388 , .Tx_Vld( RspTx_Vld ) 27389 , .Vld( Arb_Vld ) 27390 ); 27391 assign CxtRdy = Rsp_Rdy; 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( 27393 .Rx_2( u_8bb4_2 ) 27394 , .Rx_3( u_8bb4_3 ) 27395 , .Rx_4( u_8bb4_4 ) 27396 , .RxRdy( RspRdy ) 27397 , .RxVld( WrCxt ) 27398 , .Sys_Clk( Sys_Clk ) 27399 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27400 , .Sys_Clk_En( Sys_Clk_En ) 27401 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27402 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27403 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27404 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27405 , .Sys_Pwr_Idle( Pwr_Cxt_Idle ) 27406 , .Sys_Pwr_WakeUp( Pwr_Cxt_WakeUp ) 27407 , .Tx_2( u_7df2_2 ) 27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27408 , .Tx_3( u_7df2_3 ) 27409 , .Tx_4( u_7df2_4 ) 27410 , .TxRdy( CxtRdy ) 27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27411 , .TxVld( CxtVld ) 27412 ); 27413 assign u_6_RSP_IDLE = RspRdy; 27414 assign u_6_WAIT_RSP = Empty & RspRdy; 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( 27416 .Clk( Sys_Clk ) 27417 , .Clk_ClkS( Sys_Clk_ClkS ) 27418 , .Clk_En( Sys_Clk_En ) 27419 , .Clk_EnS( Sys_Clk_EnS ) 27420 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27421 , .Clk_RstN( Sys_Clk_RstN ) 27422 , .Clk_Tm( Sys_Clk_Tm ) 27423 , .Conditions_IDLE_WAIT( u_6_IDLE_WAIT ) 27424 , .Conditions_RSP_IDLE( u_6_RSP_IDLE ) 27425 , .Conditions_WAIT_RSP( u_6_WAIT_RSP ) 27426 , .CurState( u_bdb6 ) 27427 , .NextState( u_b9ec ) 27428 ); 27429 assign CurState = u_bdb6; 27430 assign RxErr_Rdy = 27431 ~ RxErr_Head & ReqTx0_Rdy 27432 | CurState == 2'b00 & ~ LoopBack & ReqTx0_Rdy 27433 | CurState == 2'b01 & Empty & RspRdy 27434 | LoopPld; 27435 rsnoc_z_H_R_G_T2_B_U_036233d4 Ibe( 27436 .CrossB1( 10'b0 ) 27437 , .Rx_Data( ReqRx_Data ) 27438 , .Rx_Head( ReqRx_Head ) 27439 , .Rx_Rdy( ReqRx_Rdy ) 27440 , .Rx_Tail( ReqRx_Tail ) 27441 , .Rx_Vld( ReqRx_Vld ) 27442 , .Sys_Clk( Sys_Clk ) 27443 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27444 , .Sys_Clk_En( Sys_Clk_En ) 27445 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27446 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27447 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27448 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27449 , .Sys_Pwr_Idle( Pwr_BusErr_Idle ) 27450 , .Sys_Pwr_WakeUp( Pwr_BusErr_WakeUp ) 27451 , .Tx_Data( RxErr_Data ) 27452 , .Tx_Head( RxErr_Head ) 27453 , .Tx_Rdy( RxErr_Rdy ) 27454 , .Tx_Tail( RxErr_Tail ) 27455 , .Tx_Vld( RxErr_Vld ) 27456 ); 27457 assign RxWord_Hdr_Addr = RxErr_Data [79:49]; 27458 assign CxtWr_AddLd0 = RxWord_Hdr_Addr [7:0]; 27459 assign CxtWr_Addr4Be = 2'b0; 27460 assign RxWord_Hdr_Echo = RxErr_Data [40:38]; 27461 assign CxtWr_Echo = RxWord_Hdr_Echo; 27462 assign CxtWr_Head = 1'b0; 27463 assign CxtWr_Len1 = RxWord_Hdr_Len1 [5:0]; 27464 assign RxWord_Hdr_Opc = RxErr_Data [92:89]; 27465 assign CxtWr_OpcT = RxWord_Hdr_Opc; 27466 assign CxtWr_RouteIdZ = 8'b0; 27467 assign ReqTx0_Data = RxErr_Data; 27468 assign ReqTx_Data = { ReqTx0_Data [107:38] , ReqTx0_Data [37:0] }; 27469 assign ReqTx0_Head = RxErr_Head; 27470 assign ReqTx_Head = ReqTx0_Head; 27471 assign ReqTx0_Tail = RxErr_Tail; 27472 assign ReqTx_Tail = ReqTx0_Tail; 27473 assign ReqTx0_Vld = RxErr_Vld & ( ~ RxErr_Head & ~ LoopPld | CurState == 2'b00 & ~ LoopBack ); 27474 assign ReqTx_Vld = ReqTx0_Vld; 27475 assign Sys_Pwr_Idle = Pwr_BusErr_Idle & Pwr_Cxt_Idle; 27476 assign Sys_Pwr_WakeUp = ReqRx_Vld; 27477 // synopsys translate_off 27478 // synthesis translate_off 27479 always @( posedge Sys_Clk ) 27480 begin 27481 if ( Sys_Clk_RstN & 1'b1 ) 27482 if ( Arb_Req == 2'b0 ) // BitCov [GRADE=1] O = 1 27483 begin end 27484 end 27485 // synthesis translate_on 27486 // synopsys translate_on 27487 // synopsys translate_off 27488 // synthesis translate_off 27489 always @( posedge Sys_Clk ) 27490 begin 27491 if ( Sys_Clk_RstN & 1'b1 ) 27492 if ( Arb_Req == 2'b01 ) // BitCov [GRADE=1] O = 1 27493 begin end 27494 end 27495 // synthesis translate_on 27496 // synopsys translate_on 27497 // synopsys translate_off 27498 // synthesis translate_off 27499 always @( posedge Sys_Clk ) 27500 begin 27501 if ( Sys_Clk_RstN & 1'b1 ) 27502 if ( Arb_Req == 2'b10 ) // BitCov [GRADE=1] O = 1 27503 begin end 27504 end 27505 // synthesis translate_on 27506 // synopsys translate_on 27507 // synopsys translate_off 27508 // synthesis translate_off 27509 rsnoc_z_H_R_G_T2_S_U_45bd45ab Ise( 27510 .Clk( Sys_Clk ) 27511 , .Clk_ClkS( Sys_Clk_ClkS ) 27512 , .Clk_En( Sys_Clk_En ) 27513 , .Clk_EnS( Sys_Clk_EnS ) 27514 , .Clk_RetRstN( Sys_Clk_RetRstN ) 27515 , .Clk_RstN( Sys_Clk_RstN ) 27516 , .Clk_Tm( Sys_Clk_Tm ) 27517 , .Rx_Data( ReqRx_Data ) 27518 , .Rx_Head( ReqRx_Head ) 27519 , .Rx_Rdy( ReqRx_Rdy ) 27520 , .Rx_Tail( ReqRx_Tail ) 27521 , .Rx_Vld( ReqRx_Vld ) 27522 , .RxAddrMask( AddrMask ) 27523 , .RxApertureHit( PathFound & SubFound ) 27524 , .RxPathHit( PathFound ) 27525 ); 27526 // synthesis translate_on 27527 // synopsys translate_on 27528 endmodule 27529 27530 `timescale 1ps/1ps 27531 module rsnoc_z_H_R_G_T2_O_U_348d615c ( 27532 Cxt_0 27533 , CxtUsed 27534 , Rdy 27535 , Req_AddLd0 27536 , Req_AddMdL 27537 , Req_Len1 27538 , Req_OpcT 27539 , Req_RouteId 27540 , Req_Strm 27541 , ReqRdy 27542 , ReqVld 27543 , Sys_Clk 27544 , Sys_Clk_ClkS 27545 , Sys_Clk_En 27546 , Sys_Clk_EnS 27547 , Sys_Clk_RetRstN 27548 , Sys_Clk_RstN 27549 , Sys_Clk_Tm 27550 , Sys_Pwr_Idle 27551 , Sys_Pwr_WakeUp 27552 ); 27553 input [31:0] Cxt_0 ; 27554 input CxtUsed ; 27555 output Rdy ; 27556 input [7:0] Req_AddLd0 ; 27557 input [22:0] Req_AddMdL ; 27558 input [5:0] Req_Len1 ; 27559 input [3:0] Req_OpcT ; 27560 input [13:0] Req_RouteId ; 27561 input Req_Strm ; 27562 input ReqRdy ; 27563 input ReqVld ; 27564 input Sys_Clk ; 27565 input Sys_Clk_ClkS ; 27566 input Sys_Clk_En ; 27567 input Sys_Clk_EnS ; 27568 input Sys_Clk_RetRstN ; 27569 input Sys_Clk_RstN ; 27570 input Sys_Clk_Tm ; 27571 output Sys_Pwr_Idle ; 27572 output Sys_Pwr_WakeUp ; 27573 assign Rdy = 1'b1; 27574 assign Sys_Pwr_Idle = 1'b1; 27575 assign Sys_Pwr_WakeUp = 1'b0; 27576 endmodule 27577 27578 `timescale 1ps/1ps 27579 module rsnoc_z_H_R_G_T2_P_U_0abfadf8 ( 27580 Cxt_AddLd0 27581 , Cxt_Addr4Be 27582 , Cxt_Echo 27583 , Cxt_Head 27584 , Cxt_Len1 27585 , Cxt_OpcT 27586 , Cxt_RouteIdZ 27587 , CxtUsed 27588 , Rx_CxtId 27589 , Rx_Head 27590 , Rx_Last 27591 , Rx_Opc 27592 , Rx_Pld 27593 , Rx_Rdy 27594 , Rx_Status 27595 , Rx_Vld 27596 , Sys_Clk 27597 , Sys_Clk_ClkS 27598 , Sys_Clk_En 27599 , Sys_Clk_EnS 27600 , Sys_Clk_RetRstN 27601 , Sys_Clk_RstN 27602 , Sys_Clk_Tm 27603 , Sys_Pwr_Idle 27604 , Sys_Pwr_WakeUp 27605 , Tx_Data 27606 , Tx_Head 27607 , Tx_Rdy 27608 , Tx_Tail 27609 , Tx_Vld 27610 , TxCxtId 27611 , TxLast 27612 ); 27613 input [7:0] Cxt_AddLd0 ; 27614 input [1:0] Cxt_Addr4Be ; 27615 input [2:0] Cxt_Echo ; 27616 input Cxt_Head ; 27617 input [5:0] Cxt_Len1 ; 27618 input [3:0] Cxt_OpcT ; 27619 input [7:0] Cxt_RouteIdZ ; 27620 input CxtUsed ; 27621 input Rx_CxtId ; 27622 input Rx_Head ; 27623 input Rx_Last ; 27624 input [3:0] Rx_Opc ; 27625 input [37:0] Rx_Pld ; 27626 output Rx_Rdy ; 27627 input [1:0] Rx_Status ; 27628 input Rx_Vld ; 27629 input Sys_Clk ; 27630 input Sys_Clk_ClkS ; 27631 input Sys_Clk_En ; 27632 input Sys_Clk_EnS ; 27633 input Sys_Clk_RetRstN ; 27634 input Sys_Clk_RstN ; 27635 input Sys_Clk_Tm ; 27636 output Sys_Pwr_Idle ; 27637 output Sys_Pwr_WakeUp ; 27638 output [107:0] Tx_Data ; 27639 output Tx_Head ; 27640 input Tx_Rdy ; 27641 output Tx_Tail ; 27642 output Tx_Vld ; 27643 output TxCxtId ; 27644 output TxLast ; 27645 wire [7:0] u_29f0 ; 27646 wire Cur_CxtId ; 27647 wire Cur_Last ; 27648 wire [3:0] Cur_Opc ; 27649 wire [37:0] Cur_Pld ; 27650 wire [1:0] Cur_Status ; 27651 wire [30:0] Hdr_Addr ; 27652 wire [2:0] Hdr_Echo ; 27653 wire [6:0] Hdr_Len1 ; 27654 wire [3:0] Hdr_Opc ; 27655 wire [13:0] Hdr_RouteId ; 27656 wire [1:0] Hdr_Status ; 27657 wire Head ; 27658 wire Tail ; 27659 wire [69:0] TxHdr ; 27660 wire [37:0] TxPld ; 27661 assign Rx_Rdy = Tx_Rdy; 27662 assign Sys_Pwr_Idle = 1'b1; 27663 assign Sys_Pwr_WakeUp = 1'b0; 27664 assign u_29f0 = Cxt_RouteIdZ; 27665 assign Hdr_RouteId = { 1'b0 , u_29f0 [7:5] , 5'b0 , u_29f0 [4:0] } | 14'b00000111100000; 27666 assign Cur_Opc = Rx_Opc; 27667 assign Hdr_Opc = Cur_Opc; 27668 assign Cur_Status = Rx_Status; 27669 assign Hdr_Status = Cur_Status; 27670 assign Hdr_Len1 = { 1'b0 , Cxt_Len1 }; 27671 assign Hdr_Addr = { 23'b10000000000000000000000 , Cxt_AddLd0 }; 27672 assign Hdr_Echo = Cxt_Echo; 27673 assign TxHdr = { 1'b0 , Hdr_RouteId , Hdr_Opc , Hdr_Status , Hdr_Len1 , Hdr_Addr , 8'b0 , Hdr_Echo }; 27674 assign Cur_Pld = Rx_Pld; 27675 assign TxPld = Cur_Pld; 27676 assign Tx_Data = { TxHdr , TxPld }; 27677 assign Head = Rx_Head; 27678 assign Tx_Head = Head; 27679 assign Cur_Last = Rx_Last; 27680 assign Tail = Cur_Last; 27681 assign Tx_Tail = Tail; 27682 assign Tx_Vld = Rx_Vld; 27683 assign Cur_CxtId = Rx_CxtId; 27684 assign TxCxtId = Cur_CxtId; 27685 assign TxLast = Cur_Last; 27686 endmodule 27687 27688 `timescale 1ps/1ps 27689 module rsnoc_z_H_R_G_T2_T_U_0abfadf8 ( 27690 AddrBase 27691 , Cmd_Echo 27692 , Cmd_KeyId 27693 , Cmd_Len1 27694 , Cmd_Lock 27695 , Cmd_OpcT 27696 , Cmd_RawAddr 27697 , Cmd_RouteId 27698 , Cmd_Status 27699 , Cmd_User 27700 , HitId 27701 , Pld_Data 27702 , Pld_Last 27703 , Rdy 27704 , Rx_Data 27705 , Rx_Head 27706 , Rx_Rdy 27707 , Rx_Tail 27708 , Rx_Vld 27709 , Sys_Clk 27710 , Sys_Clk_ClkS 27711 , Sys_Clk_En 27712 , Sys_Clk_EnS 27713 , Sys_Clk_RetRstN 27714 , Sys_Clk_RstN 27715 , Sys_Clk_Tm 27716 , Sys_Pwr_Idle 27717 , Sys_Pwr_WakeUp 27718 , Vld 27719 ); 27720 input [29:0] AddrBase ; 27721 output [2:0] Cmd_Echo ; 27722 output Cmd_KeyId ; 27723 output [5:0] Cmd_Len1 ; 27724 output Cmd_Lock ; 27725 output [3:0] Cmd_OpcT ; 27726 output [31:0] Cmd_RawAddr ; 27727 output [13:0] Cmd_RouteId ; 27728 output [1:0] Cmd_Status ; 27729 output [7:0] Cmd_User ; 27730 input HitId ; 27731 output [37:0] Pld_Data ; 27732 output Pld_Last ; 27733 input Rdy ; 27734 input [107:0] Rx_Data ; 27735 input Rx_Head ; 27736 output Rx_Rdy ; 27737 input Rx_Tail ; 27738 input Rx_Vld ; 27739 input Sys_Clk ; 27740 input Sys_Clk_ClkS ; 27741 input Sys_Clk_En ; 27742 input Sys_Clk_EnS ; 27743 input Sys_Clk_RetRstN ; 27744 input Sys_Clk_RstN ; 27745 input Sys_Clk_Tm ; 27746 output Sys_Pwr_Idle ; 27747 output Sys_Pwr_WakeUp ; 27748 output Vld ; 27749 wire [2:0] u_42be_1 ; 27750 wire [31:0] u_42be_10 ; 27751 wire [13:0] u_42be_11 ; 27752 wire [1:0] u_42be_13 ; 27753 wire [7:0] u_42be_15 ; 27754 wire u_42be_6 ; 27755 wire [5:0] u_42be_7 ; 27756 wire u_42be_8 ; 27757 wire [3:0] u_42be_9 ; 27758 wire [37:0] u_6846_0 ; 27759 wire u_6846_1 ; 27760 wire [37:0] u_b984_0 ; 27761 wire u_b984_1 ; 27762 wire [2:0] u_ca1c_1 ; 27763 wire [31:0] u_ca1c_10 ; 27764 wire [13:0] u_ca1c_11 ; 27765 wire [1:0] u_ca1c_13 ; 27766 wire [7:0] u_ca1c_15 ; 27767 wire u_ca1c_6 ; 27768 wire [5:0] u_ca1c_7 ; 27769 wire u_ca1c_8 ; 27770 wire [3:0] u_ca1c_9 ; 27771 wire [6:0] u_e4c6 ; 27772 wire [2:0] CmdIn_Echo ; 27773 wire CmdIn_KeyId ; 27774 wire [5:0] CmdIn_Len1 ; 27775 wire CmdIn_Lock ; 27776 wire [3:0] CmdIn_OpcT ; 27777 wire [31:0] CmdIn_RawAddr ; 27778 wire [13:0] CmdIn_RouteId ; 27779 wire [1:0] CmdIn_Status ; 27780 wire [7:0] CmdIn_User ; 27781 wire [37:0] PldIn_Data ; 27782 wire PldIn_Last ; 27783 wire PldVld ; 27784 wire Pwr_Pipe_Idle ; 27785 wire Pwr_Pipe_WakeUp ; 27786 wire [29:0] Req_BaseAddr ; 27787 wire [37:0] Req_Data ; 27788 wire [2:0] Req_Echo ; 27789 wire Req_KeyId ; 27790 wire Req_Last ; 27791 wire [5:0] Req_Len1 ; 27792 wire Req_Lock ; 27793 wire [3:0] Req_OpcT ; 27794 wire [31:0] Req_RawAddr ; 27795 wire [13:0] Req_RouteId ; 27796 wire [1:0] Req_Status ; 27797 wire [7:0] Req_User ; 27798 assign Req_Echo = Rx_Data [40:38]; 27799 assign CmdIn_Echo = Req_Echo; 27800 assign u_ca1c_1 = CmdIn_Echo; 27801 assign Req_BaseAddr = AddrBase; 27802 assign Req_RawAddr = 27803 ( { 1'b0 , Rx_Data [79:49] } | { Req_BaseAddr , 2'b00 } ) 27804 & { 25'b1111111111111111111111111 , ~ { 7 { 1'b0 } } } 27805 & ~ { 32 { 1'b0 } }; 27806 assign CmdIn_RawAddr = Req_RawAddr; 27807 assign u_ca1c_10 = CmdIn_RawAddr; 27808 assign Req_RouteId = Rx_Data [106:93]; 27809 assign CmdIn_RouteId = Req_RouteId; 27810 assign u_ca1c_11 = CmdIn_RouteId; 27811 assign Req_Status = Rx_Data [88:87]; 27812 assign CmdIn_Status = Req_Status; 27813 assign u_ca1c_13 = CmdIn_Status; 27814 assign Req_User = Rx_Data [48:41]; 27815 assign CmdIn_User = Req_User; 27816 assign u_ca1c_15 = CmdIn_User; 27817 assign Req_KeyId = HitId; 27818 assign CmdIn_KeyId = Req_KeyId; 27819 assign u_ca1c_6 = CmdIn_KeyId; 27820 assign u_e4c6 = Rx_Data [86:80] & ~ { 7 { 1'b0 } }; 27821 assign Req_Len1 = u_e4c6 [5:0]; 27822 assign CmdIn_Len1 = Req_Len1; 27823 assign u_ca1c_7 = CmdIn_Len1; 27824 assign Req_Lock = Rx_Data [107]; 27825 assign CmdIn_Lock = Req_Lock; 27826 assign u_ca1c_8 = CmdIn_Lock; 27827 assign Req_OpcT = Rx_Data [92:89]; 27828 assign CmdIn_OpcT = Req_OpcT; 27829 assign u_ca1c_9 = CmdIn_OpcT; 27830 rsnoc_z_H_R_U_P_N_17116f53_A030000161432140208 Icp( 27831 .Rx_1( u_ca1c_1 ) 27832 , .Rx_10( u_ca1c_10 ) 27833 , .Rx_11( u_ca1c_11 ) 27834 , .Rx_13( u_ca1c_13 ) 27835 , .Rx_15( u_ca1c_15 ) 27836 , .Rx_6( u_ca1c_6 ) 27837 , .Rx_7( u_ca1c_7 ) 27838 , .Rx_8( u_ca1c_8 ) 27839 , .Rx_9( u_ca1c_9 ) 27840 , .RxRdy( Rx_Rdy ) 27841 , .RxVld( Rx_Vld ) 27842 , .Sys_Clk( Sys_Clk ) 27843 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27844 , .Sys_Clk_En( Sys_Clk_En ) 27845 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27846 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27847 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27848 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27849 , .Sys_Pwr_Idle( Pwr_Pipe_Idle ) 27850 , .Sys_Pwr_WakeUp( Pwr_Pipe_WakeUp ) 27851 , .Tx_1( u_42be_1 ) 27852 , .Tx_10( u_42be_10 ) 27853 , .Tx_11( u_42be_11 ) 27854 , .Tx_13( u_42be_13 ) 27855 , .Tx_15( u_42be_15 ) 27856 , .Tx_6( u_42be_6 ) 27857 , .Tx_7( u_42be_7 ) 27858 , .Tx_8( u_42be_8 ) 27859 , .Tx_9( u_42be_9 ) 27860 , .TxRdy( Rdy ) 27861 , .TxVld( Vld ) 27862 ); 27863 assign Cmd_Echo = u_42be_1; 27864 assign Cmd_KeyId = u_42be_6; 27865 assign Cmd_Len1 = u_42be_7; 27866 assign Cmd_Lock = u_42be_8; 27867 assign Cmd_OpcT = u_42be_9; 27868 assign Cmd_RawAddr = u_42be_10; 27869 assign Cmd_RouteId = u_42be_11; 27870 assign Cmd_Status = u_42be_13; 27871 assign Cmd_User = u_42be_15; 27872 assign Req_Data = Rx_Data [37:0]; 27873 assign PldIn_Data = Req_Data; 27874 assign u_b984_0 = PldIn_Data; 27875 assign Req_Last = Rx_Tail; 27876 assign PldIn_Last = Req_Last; 27877 assign u_b984_1 = PldIn_Last; 27878 rsnoc_z_H_R_U_P_N_7720665d_A381 Ipp( 27879 .Rx_0( u_b984_0 ) 27880 , .Rx_1( u_b984_1 ) 27881 , .RxRdy( ) 27882 , .RxVld( Rx_Vld ) 27883 , .Sys_Clk( Sys_Clk ) 27884 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 27885 , .Sys_Clk_En( Sys_Clk_En ) 27886 , .Sys_Clk_EnS( Sys_Clk_EnS ) 27887 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 27888 , .Sys_Clk_RstN( Sys_Clk_RstN ) 27889 , .Sys_Clk_Tm( Sys_Clk_Tm ) 27890 , .Sys_Pwr_Idle( ) 27891 , .Sys_Pwr_WakeUp( ) 27892 , .Tx_0( u_6846_0 ) 27893 , .Tx_1( u_6846_1 ) 27894 , .TxRdy( Rdy ) 27895 , .TxVld( PldVld ) 27896 ); 27897 assign Pld_Data = u_6846_0; 27898 assign Pld_Last = u_6846_1; 27899 assign Sys_Pwr_Idle = Pwr_Pipe_Idle; 27900 assign Sys_Pwr_WakeUp = 1'b0; 27901 endmodule 27902 27903 `timescale 1ps/1ps 27904 module rsnoc_z_H_R_G_T2_U_U_f2473f73 ( 27905 Gen_Req_Addr 27906 , Gen_Req_Be 27907 , Gen_Req_BurstType 27908 , Gen_Req_Data 27909 , Gen_Req_Last 27910 , Gen_Req_Len1 27911 , Gen_Req_Lock 27912 , Gen_Req_Opc 27913 , Gen_Req_Rdy 27914 , Gen_Req_SeqUnOrdered 27915 , Gen_Req_SeqUnique 27916 , Gen_Req_User 27917 , Gen_Req_Vld 27918 , Gen_Rsp_Data 27919 , Gen_Rsp_Last 27920 , Gen_Rsp_Rdy 27921 , Gen_Rsp_SeqUnOrdered 27922 , Gen_Rsp_Status 27923 , Gen_Rsp_Vld 27924 , IdInfo_0_AddrBase 27925 , IdInfo_0_AddrMask 27926 , IdInfo_0_Debug 27927 , IdInfo_0_Id 27928 , IdInfo_1_AddrBase 27929 , IdInfo_1_AddrMask 27930 , IdInfo_1_Debug 27931 , IdInfo_1_Id 27932 , Load 27933 , NoPendingTrans 27934 , Rx_Data 27935 , Rx_Head 27936 , Rx_Rdy 27937 , Rx_Tail 27938 , Rx_Vld 27939 , Sys_Clk 27940 , Sys_Clk_ClkS 27941 , Sys_Clk_En 27942 , Sys_Clk_EnS 27943 , Sys_Clk_RetRstN 27944 , Sys_Clk_RstN 27945 , Sys_Clk_Tm 27946 , Sys_Pwr_Idle 27947 , Sys_Pwr_WakeUp 27948 , Translation_0_Aperture 27949 , Translation_0_Id 27950 , Translation_0_PathFound 27951 , Translation_0_SubFound 27952 , Tx_Data 27953 , Tx_Head 27954 , Tx_Rdy 27955 , Tx_Tail 27956 , Tx_Vld 27957 , WakeUp_Other 27958 , WakeUp_Rx 27959 ); 27960 output [31:0] Gen_Req_Addr ; 27961 output [3:0] Gen_Req_Be ; 27962 output Gen_Req_BurstType ; 27963 output [31:0] Gen_Req_Data ; 27964 output Gen_Req_Last ; 27965 output [5:0] Gen_Req_Len1 ; 27966 output Gen_Req_Lock ; 27967 output [2:0] Gen_Req_Opc ; 27968 input Gen_Req_Rdy ; 27969 output Gen_Req_SeqUnOrdered ; 27970 output Gen_Req_SeqUnique ; 27971 output [7:0] Gen_Req_User ; 27972 output Gen_Req_Vld ; 27973 input [31:0] Gen_Rsp_Data ; 27974 input Gen_Rsp_Last ; 27975 output Gen_Rsp_Rdy ; 27976 input Gen_Rsp_SeqUnOrdered ; 27977 input [1:0] Gen_Rsp_Status ; 27978 input Gen_Rsp_Vld ; 27979 input [29:0] IdInfo_0_AddrBase ; 27980 input [29:0] IdInfo_0_AddrMask ; 27981 input IdInfo_0_Debug ; 27982 output IdInfo_0_Id ; 27983 input [29:0] IdInfo_1_AddrBase ; 27984 input [29:0] IdInfo_1_AddrMask ; 27985 input IdInfo_1_Debug ; 27986 output IdInfo_1_Id ; 27987 output [1:0] Load ; 27988 output NoPendingTrans ; 27989 input [107:0] Rx_Data ; 27990 input Rx_Head ; 27991 output Rx_Rdy ; 27992 input Rx_Tail ; 27993 input Rx_Vld ; 27994 input Sys_Clk ; 27995 input Sys_Clk_ClkS ; 27996 input Sys_Clk_En ; 27997 input Sys_Clk_EnS ; 27998 input Sys_Clk_RetRstN ; 27999 input Sys_Clk_RstN ; 28000 input Sys_Clk_Tm ; 28001 output Sys_Pwr_Idle ; 28002 output Sys_Pwr_WakeUp ; 28003 output [8:0] Translation_0_Aperture ; 28004 input Translation_0_Id ; 28005 input Translation_0_PathFound ; 28006 input Translation_0_SubFound ; 28007 output [107:0] Tx_Data ; 28008 output Tx_Head ; 28009 input Tx_Rdy ; 28010 output Tx_Tail ; 28011 output Tx_Vld ; 28012 output WakeUp_Other ; 28013 output WakeUp_Rx ; 28014 wire [31:0] u_Req_Addr ; 28015 wire [3:0] u_Req_Be ; 28016 wire u_Req_BurstType ; 28017 wire [31:0] u_Req_Data ; 28018 wire u_Req_Last ; 28019 wire [5:0] u_Req_Len1 ; 28020 wire u_Req_Lock ; 28021 wire [2:0] u_Req_Opc ; 28022 wire u_Req_Rdy ; 28023 wire u_Req_SeqUnOrdered ; 28024 wire u_Req_SeqUnique ; 28025 wire [7:0] u_Req_User ; 28026 wire u_Req_Vld ; 28027 wire [31:0] u_Rsp_Data ; 28028 wire u_Rsp_Last ; 28029 wire u_Rsp_Rdy ; 28030 wire u_Rsp_SeqUnOrdered ; 28031 wire [1:0] u_Rsp_Status ; 28032 wire u_Rsp_Vld ; 28033 wire u_236 ; 28034 wire [69:0] u_2c5e ; 28035 reg [7:0] u_31e2 ; 28036 reg [5:0] u_3d2e ; 28037 wire u_43f9 ; 28038 reg [31:0] u_4e00 ; 28039 wire u_5717 ; 28040 wire u_5ddf ; 28041 wire u_70_Idle ; 28042 wire u_70_WakeUp ; 28043 reg [7:0] u_703a ; 28044 reg [2:0] u_77fb ; 28045 wire u_a9bf_Data_Datum0_Be ; 28046 wire [7:0] u_a9bf_Data_Datum0_Byte ; 28047 wire u_a9bf_Data_Datum1_Be ; 28048 wire [7:0] u_a9bf_Data_Datum1_Byte ; 28049 wire u_a9bf_Data_Datum2_Be ; 28050 wire [7:0] u_a9bf_Data_Datum2_Byte ; 28051 wire u_a9bf_Data_Datum3_Be ; 28052 wire [7:0] u_a9bf_Data_Datum3_Byte ; 28053 wire u_a9bf_Data_Err ; 28054 wire u_a9bf_Data_Last ; 28055 wire [30:0] u_a9bf_Hdr_Addr ; 28056 wire [2:0] u_a9bf_Hdr_Echo ; 28057 wire [6:0] u_a9bf_Hdr_Len1 ; 28058 wire u_a9bf_Hdr_Lock ; 28059 wire [3:0] u_a9bf_Hdr_Opc ; 28060 wire [13:0] u_a9bf_Hdr_RouteId ; 28061 wire [1:0] u_a9bf_Hdr_Status ; 28062 wire [7:0] u_a9bf_Hdr_User ; 28063 wire [1:0] u_b16a ; 28064 wire [31:0] u_b46 ; 28065 wire u_bb4d ; 28066 wire [3:0] u_c4ee ; 28067 wire [31:0] u_cb9b_0 ; 28068 wire u_cb9b_1 ; 28069 wire [2:0] u_cb9b_11 ; 28070 wire u_cb9b_17 ; 28071 wire [7:0] u_cb9b_19 ; 28072 wire [37:0] u_cb9b_2 ; 28073 wire u_cb9b_4 ; 28074 wire u_cb9b_6 ; 28075 wire u_cb9b_7 ; 28076 wire [5:0] u_cb9b_8 ; 28077 wire u_cb9b_9 ; 28078 reg [3:0] u_cc5c ; 28079 wire [31:0] u_d4d9_0 ; 28080 wire u_d4d9_1 ; 28081 wire [2:0] u_d4d9_11 ; 28082 wire u_d4d9_14 ; 28083 wire u_d4d9_15 ; 28084 wire u_d4d9_17 ; 28085 wire [7:0] u_d4d9_19 ; 28086 wire [37:0] u_d4d9_2 ; 28087 wire u_d4d9_4 ; 28088 wire u_d4d9_6 ; 28089 wire u_d4d9_7 ; 28090 wire [5:0] u_d4d9_8 ; 28091 wire u_d4d9_9 ; 28092 reg [3:0] u_da22 ; 28093 wire [13:0] u_f14a ; 28094 reg [1:0] u_f3f5 ; 28095 wire u_fd35_Data_Datum0_Be ; 28096 wire [7:0] u_fd35_Data_Datum0_Byte ; 28097 wire u_fd35_Data_Datum1_Be ; 28098 wire [7:0] u_fd35_Data_Datum1_Byte ; 28099 wire u_fd35_Data_Datum2_Be ; 28100 wire [7:0] u_fd35_Data_Datum2_Byte ; 28101 wire u_fd35_Data_Datum3_Be ; 28102 wire [7:0] u_fd35_Data_Datum3_Byte ; 28103 wire u_fd35_Data_Err ; 28104 wire u_fd35_Data_Last ; 28105 wire [30:0] u_fd35_Hdr_Addr ; 28106 wire [2:0] u_fd35_Hdr_Echo ; 28107 wire [6:0] u_fd35_Hdr_Len1 ; 28108 wire u_fd35_Hdr_Lock ; 28109 wire [3:0] u_fd35_Hdr_Opc ; 28110 wire [13:0] u_fd35_Hdr_RouteId ; 28111 wire [1:0] u_fd35_Hdr_Status ; 28112 wire [7:0] u_fd35_Hdr_User ; 28113 wire CtxFreeId ; 28114 wire [31:0] Cxt_0 ; 28115 wire CxtEn ; 28116 wire CxtFreeVld ; 28117 wire CxtId ; 28118 wire [7:0] CxtPkt_AddLd0 ; 28119 wire [1:0] CxtPkt_Addr4Be ; 28120 wire [2:0] CxtPkt_Echo ; 28121 wire CxtPkt_Head ; 28122 wire [5:0] CxtPkt_Len1 ; 28123 wire [3:0] CxtPkt_OpcT ; 28124 wire [7:0] CxtPkt_RouteIdZ ; 28125 wire CxtRdy ; 28126 wire [1:0] CxtRsp1_Addr4Be ; 28127 wire CxtRsp1_Head ; 28128 wire [5:0] CxtRsp1_Len1 ; 28129 wire [3:0] CxtRsp1_OpcT ; 28130 wire CxtUsed ; 28131 wire Dbg_Rx_Data_Datum0_Be ; 28132 wire [7:0] Dbg_Rx_Data_Datum0_Byte ; 28133 wire Dbg_Rx_Data_Datum1_Be ; 28134 wire [7:0] Dbg_Rx_Data_Datum1_Byte ; 28135 wire Dbg_Rx_Data_Datum2_Be ; 28136 wire [7:0] Dbg_Rx_Data_Datum2_Byte ; 28137 wire Dbg_Rx_Data_Datum3_Be ; 28138 wire [7:0] Dbg_Rx_Data_Datum3_Byte ; 28139 wire Dbg_Rx_Data_Err ; 28140 wire Dbg_Rx_Data_Last ; 28141 wire [30:0] Dbg_Rx_Hdr_Addr ; 28142 wire [2:0] Dbg_Rx_Hdr_Echo ; 28143 wire [6:0] Dbg_Rx_Hdr_Len1 ; 28144 wire Dbg_Rx_Hdr_Lock ; 28145 wire [3:0] Dbg_Rx_Hdr_Opc ; 28146 wire [13:0] Dbg_Rx_Hdr_RouteId ; 28147 wire [1:0] Dbg_Rx_Hdr_Status ; 28148 wire [7:0] Dbg_Rx_Hdr_User ; 28149 wire Dbg_Tx_Data_Datum0_Be ; 28150 wire [7:0] Dbg_Tx_Data_Datum0_Byte ; 28151 wire Dbg_Tx_Data_Datum1_Be ; 28152 wire [7:0] Dbg_Tx_Data_Datum1_Byte ; 28153 wire Dbg_Tx_Data_Datum2_Be ; 28154 wire [7:0] Dbg_Tx_Data_Datum2_Byte ; 28155 wire Dbg_Tx_Data_Datum3_Be ; 28156 wire [7:0] Dbg_Tx_Data_Datum3_Byte ; 28157 wire Dbg_Tx_Data_Err ; 28158 wire Dbg_Tx_Data_Last ; 28159 wire [30:0] Dbg_Tx_Hdr_Addr ; 28160 wire [2:0] Dbg_Tx_Hdr_Echo ; 28161 wire [6:0] Dbg_Tx_Hdr_Len1 ; 28162 wire Dbg_Tx_Hdr_Lock ; 28163 wire [3:0] Dbg_Tx_Hdr_Opc ; 28164 wire [13:0] Dbg_Tx_Hdr_RouteId ; 28165 wire [1:0] Dbg_Tx_Hdr_Status ; 28166 wire [7:0] Dbg_Tx_Hdr_User ; 28167 wire Empty ; 28168 wire [7:0] ErrCxtRd_AddLd0 ; 28169 wire [1:0] ErrCxtRd_Addr4Be ; 28170 wire [2:0] ErrCxtRd_Echo ; 28171 wire ErrCxtRd_Head ; 28172 wire [5:0] ErrCxtRd_Len1 ; 28173 wire [3:0] ErrCxtRd_OpcT ; 28174 wire [7:0] ErrCxtRd_RouteIdZ ; 28175 wire [7:0] ErrCxtWr_AddLd0 ; 28176 wire [1:0] ErrCxtWr_Addr4Be ; 28177 wire [2:0] ErrCxtWr_Echo ; 28178 wire ErrCxtWr_Head ; 28179 wire [5:0] ErrCxtWr_Len1 ; 28180 wire [3:0] ErrCxtWr_OpcT ; 28181 wire [7:0] ErrCxtWr_RouteIdZ ; 28182 wire ErrWrCxt ; 28183 wire [31:0] GenLcl_Req_Addr ; 28184 wire [3:0] GenLcl_Req_Be ; 28185 wire GenLcl_Req_BurstType ; 28186 wire [31:0] GenLcl_Req_Data ; 28187 wire GenLcl_Req_Last ; 28188 wire [5:0] GenLcl_Req_Len1 ; 28189 wire GenLcl_Req_Lock ; 28190 wire [2:0] GenLcl_Req_Opc ; 28191 wire GenLcl_Req_Rdy ; 28192 wire GenLcl_Req_SeqUnOrdered ; 28193 wire GenLcl_Req_SeqUnique ; 28194 wire [7:0] GenLcl_Req_User ; 28195 wire GenLcl_Req_Vld ; 28196 wire [31:0] GenLcl_Rsp_Data ; 28197 wire GenLcl_Rsp_Last ; 28198 wire GenLcl_Rsp_Rdy ; 28199 wire GenLcl_Rsp_SeqUnOrdered ; 28200 wire [1:0] GenLcl_Rsp_Status ; 28201 wire GenLcl_Rsp_Vld ; 28202 wire [3:0] GenLclReqBe ; 28203 wire [31:0] GenLclReqData ; 28204 wire IllRsp ; 28205 wire [37:0] MyData ; 28206 wire [35:0] MyDatum ; 28207 wire NextRsp1 ; 28208 wire NextTrn ; 28209 wire NextTxPkt ; 28210 wire NullBe ; 28211 wire NullBePld ; 28212 wire OrdRdy ; 28213 wire [31:0] PipeIn_Addr ; 28214 wire PipeIn_BurstType ; 28215 wire [37:0] PipeIn_Data ; 28216 wire PipeIn_Fail ; 28217 wire PipeIn_Head ; 28218 wire PipeIn_Last ; 28219 wire [5:0] PipeIn_Len1 ; 28220 wire PipeIn_Lock ; 28221 reg [2:0] PipeIn_Opc ; 28222 wire PipeIn_Urg ; 28223 wire [7:0] PipeIn_User ; 28224 wire [31:0] PipeOut_Addr ; 28225 wire PipeOut_BurstType ; 28226 wire [37:0] PipeOut_Data ; 28227 wire PipeOut_Fail ; 28228 wire PipeOut_Head ; 28229 wire PipeOut_Last ; 28230 wire [5:0] PipeOut_Len1 ; 28231 wire PipeOut_Lock ; 28232 wire [2:0] PipeOut_Opc ; 28233 wire PipeOut_SeqUnOrdered ; 28234 wire PipeOut_SeqUnique ; 28235 wire PipeOut_Urg ; 28236 wire [7:0] PipeOut_User ; 28237 wire PipeOutHead ; 28238 wire PipeOutRdy ; 28239 wire PipeOutVld ; 28240 wire [37:0] Pld_Data ; 28241 wire Pld_Last ; 28242 wire PostRdy ; 28243 wire PostVld ; 28244 wire Pwr_CxtAlloc_Idle ; 28245 wire Pwr_CxtAlloc_WakeUp ; 28246 wire Pwr_Err_Idle ; 28247 wire Pwr_Err_WakeUp ; 28248 wire Pwr_FwdPostAlloc_Idle ; 28249 wire Pwr_FwdPostAlloc_WakeUp ; 28250 wire Pwr_RspPipe_Idle ; 28251 wire Pwr_RspPipe_WakeUp ; 28252 wire Pwr_Trn_Idle ; 28253 wire Pwr_Trn_WakeUp ; 28254 wire [7:0] Req1_AddLd0 ; 28255 wire [22:0] Req1_AddMdL ; 28256 wire [31:0] Req1_AddNttp ; 28257 wire [31:0] Req1_Addr ; 28258 wire [1:0] Req1_Addr4Be ; 28259 wire Req1_BurstType ; 28260 wire [2:0] Req1_Echo ; 28261 wire Req1_Fail ; 28262 wire Req1_KeyId ; 28263 wire [5:0] Req1_Len1 ; 28264 wire Req1_Lock ; 28265 reg [2:0] Req1_Opc ; 28266 wire [3:0] Req1_OpcT ; 28267 wire [31:0] Req1_RawAddr ; 28268 wire [13:0] Req1_RouteId ; 28269 wire [7:0] Req1_RouteIdZ ; 28270 wire [1:0] Req1_Status ; 28271 wire Req1_Urg ; 28272 wire [7:0] Req1_User ; 28273 reg ReqHead ; 28274 wire ReqRdy ; 28275 wire ReqVld ; 28276 wire [3:0] Rsp_Be ; 28277 wire [31:0] Rsp_Data ; 28278 wire Rsp_DataErr ; 28279 wire Rsp_DataLast ; 28280 wire Rsp_Head ; 28281 wire Rsp_Last ; 28282 wire [3:0] Rsp_OpcT ; 28283 wire [37:0] Rsp_Pld ; 28284 wire Rsp_Rdy ; 28285 reg [1:0] Rsp_Status ; 28286 wire Rsp_Vld ; 28287 wire [31:0] Rsp0_Data ; 28288 wire Rsp0_Last ; 28289 wire Rsp0_Rdy ; 28290 wire [1:0] Rsp0_Status ; 28291 wire Rsp0_Vld ; 28292 wire [31:0] Rsp1_Data ; 28293 wire Rsp1_Head ; 28294 wire Rsp1_Last ; 28295 wire Rsp1_Rdy ; 28296 wire [1:0] Rsp1_Status ; 28297 wire Rsp1_Vld ; 28298 wire [1:0] Rsp2_Status ; 28299 wire [3:0] RspBe ; 28300 wire [107:0] RxErr_Data ; 28301 wire RxErr_Head ; 28302 wire RxErr_Rdy ; 28303 wire RxErr_Tail ; 28304 wire RxErr_Vld ; 28305 wire [107:0] RxIn_Data ; 28306 wire RxIn_Head ; 28307 wire RxIn_Rdy ; 28308 wire RxIn_Tail ; 28309 wire RxIn_Vld ; 28310 wire [37:0] RxInData ; 28311 wire [107:0] RxInt_Data ; 28312 wire RxInt_Head ; 28313 wire RxInt_Rdy ; 28314 wire RxInt_Tail ; 28315 wire RxInt_Vld ; 28316 wire RxPkt_Head ; 28317 wire RxPkt_Last ; 28318 wire [3:0] RxPkt_Opc ; 28319 wire [37:0] RxPkt_Pld ; 28320 wire RxPkt_Rdy ; 28321 wire [1:0] RxPkt_Status ; 28322 wire RxPkt_Vld ; 28323 wire TrnGate ; 28324 wire TrnRdy ; 28325 wire TrnVld ; 28326 wire [37:0] TxBypData ; 28327 wire [107:0] TxErr_Data ; 28328 wire TxErr_Head ; 28329 wire TxErr_Rdy ; 28330 wire TxErr_Tail ; 28331 wire TxErr_Vld ; 28332 wire [107:0] TxIn_Data ; 28333 wire TxIn_Head ; 28334 wire TxIn_Rdy ; 28335 wire TxIn_Tail ; 28336 wire TxIn_Vld ; 28337 wire [107:0] TxLcl_Data ; 28338 wire TxLcl_Head ; 28339 wire TxLcl_Rdy ; 28340 wire TxLcl_Tail ; 28341 wire TxLcl_Vld ; 28342 wire [107:0] TxPkt_Data ; 28343 wire TxPkt_Head ; 28344 wire TxPkt_Rdy ; 28345 wire TxPkt_Tail ; 28346 wire TxPkt_Vld ; 28347 wire TxPktCxtId ; 28348 wire TxPktLast ; 28349 wire WrapGn ; 28350 wire WrapTrRd ; 28351 wire WrapTrWr ; 28352 reg [1:0] Load ; 28353 reg NoPendingTrans ; 28354 reg dontStop ; 28355 wire [2:0] uPipeIn_Opc_caseSel ; 28356 wire [4:0] uReq1_Opc_caseSel ; 28357 wire [4:0] uRsp_Status_caseSel ; 28358 wire uu_4e00_caseSel ; 28359 wire [1:0] uu_cc5c_caseSel ; 28360 assign NextTrn = TrnVld & TrnRdy; 28361 assign ErrCxtRd_AddLd0 = Cxt_0 [18:11]; 28362 assign ErrCxtRd_Addr4Be = Cxt_0 [9:8]; 28363 assign ErrCxtRd_Echo = Cxt_0 [25:23]; 28364 assign ErrCxtRd_Head = Cxt_0 [10]; 28365 assign ErrCxtRd_Len1 = Cxt_0 [31:26]; 28366 assign ErrCxtRd_OpcT = Cxt_0 [22:19]; 28367 assign ErrCxtRd_RouteIdZ = Cxt_0 [7:0]; 28368 rsnoc_z_H_R_T_P_U_U_18449ea0 Irspp( 28369 .Rx_Data( TxPkt_Data ) 28370 , .Rx_Head( TxPkt_Head ) 28371 , .Rx_Rdy( TxPkt_Rdy ) 28372 , .Rx_Tail( TxPkt_Tail ) 28373 , .Rx_Vld( TxPkt_Vld ) 28374 , .Sys_Clk( Sys_Clk ) 28375 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28376 , .Sys_Clk_En( Sys_Clk_En ) 28377 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28378 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28379 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28380 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28381 , .Sys_Pwr_Idle( Pwr_RspPipe_Idle ) 28382 , .Sys_Pwr_WakeUp( Pwr_RspPipe_WakeUp ) 28383 , .Tx_Data( TxErr_Data ) 28384 , .Tx_Head( TxErr_Head ) 28385 , .Tx_Rdy( TxErr_Rdy ) 28386 , .Tx_Tail( TxErr_Tail ) 28387 , .Tx_Vld( TxErr_Vld ) 28388 , .WakeUp_Rx( ) 28389 ); 28390 assign Empty = CxtUsed == 1'b0 & Pwr_RspPipe_Idle & Pwr_Trn_Idle & Pwr_FwdPostAlloc_Idle; 28391 assign RxInt_Data = Rx_Data; 28392 assign u_2c5e = RxInt_Data [107:38]; 28393 assign RxInData = RxInt_Data [37:0]; 28394 assign RxIn_Data = 28395 { { u_2c5e [69] 28396 , u_2c5e [68:55] 28397 , u_2c5e [54:51] 28398 , u_2c5e [50:49] 28399 , u_2c5e [48:42] 28400 , u_2c5e [41:11] 28401 , u_2c5e [10:3] 28402 , u_2c5e [2:0] 28403 } 28404 , 28405 RxInData 28406 }; 28407 assign RxInt_Head = Rx_Head; 28408 assign RxIn_Head = RxInt_Head; 28409 assign RxInt_Tail = Rx_Tail; 28410 assign RxIn_Tail = RxInt_Tail; 28411 assign RxInt_Vld = Rx_Vld; 28412 assign RxIn_Vld = RxInt_Vld; 28413 assign TxLcl_Rdy = Tx_Rdy; 28414 assign TxIn_Rdy = TxLcl_Rdy; 28415 rsnoc_z_H_R_G_T2_F_U_0abfadf8 If( 28416 .AddrMask( IdInfo_0_AddrMask ) 28417 , .CxtRd_AddLd0( ErrCxtRd_AddLd0 ) 28418 , .CxtRd_Addr4Be( ErrCxtRd_Addr4Be ) 28419 , .CxtRd_Echo( ErrCxtRd_Echo ) 28420 , .CxtRd_Head( ErrCxtRd_Head ) 28421 , .CxtRd_Len1( ErrCxtRd_Len1 ) 28422 , .CxtRd_OpcT( ErrCxtRd_OpcT ) 28423 , .CxtRd_RouteIdZ( ErrCxtRd_RouteIdZ ) 28424 , .CxtWr_AddLd0( ErrCxtWr_AddLd0 ) 28425 , .CxtWr_Addr4Be( ErrCxtWr_Addr4Be ) 28426 , .CxtWr_Echo( ErrCxtWr_Echo ) 28427 , .CxtWr_Head( ErrCxtWr_Head ) 28428 , .CxtWr_Len1( ErrCxtWr_Len1 ) 28429 , .CxtWr_OpcT( ErrCxtWr_OpcT ) 28430 , .CxtWr_RouteIdZ( ErrCxtWr_RouteIdZ ) 28431 , .Debug( IdInfo_0_Debug ) 28432 , .Empty( Empty ) 28433 , .PathFound( Translation_0_PathFound ) 28434 , .ReqRx_Data( RxIn_Data ) 28435 , .ReqRx_Head( RxIn_Head ) 28436 , .ReqRx_Rdy( RxIn_Rdy ) 28437 , .ReqRx_Tail( RxIn_Tail ) 28438 , .ReqRx_Vld( RxIn_Vld ) 28439 , .ReqTx_Data( RxErr_Data ) 28440 , .ReqTx_Head( RxErr_Head ) 28441 , .ReqTx_Rdy( RxErr_Rdy ) 28442 , .ReqTx_Tail( RxErr_Tail ) 28443 , .ReqTx_Vld( RxErr_Vld ) 28444 , .RspRx_Data( TxErr_Data ) 28445 , .RspRx_Head( TxErr_Head ) 28446 , .RspRx_Rdy( TxErr_Rdy ) 28447 , .RspRx_Tail( TxErr_Tail ) 28448 , .RspRx_Vld( TxErr_Vld ) 28449 , .RspTx_Data( TxIn_Data ) 28450 , .RspTx_Head( TxIn_Head ) 28451 , .RspTx_Rdy( TxIn_Rdy ) 28452 , .RspTx_Tail( TxIn_Tail ) 28453 , .RspTx_Vld( TxIn_Vld ) 28454 , .SubFound( Translation_0_SubFound ) 28455 , .Sys_Clk( Sys_Clk ) 28456 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 28457 , .Sys_Clk_En( Sys_Clk_En ) 28458 , .Sys_Clk_EnS( Sys_Clk_EnS ) 28459 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 28460 , .Sys_Clk_RstN( Sys_Clk_RstN ) 28461 , .Sys_Clk_Tm( Sys_Clk_Tm ) 28462 , .Sys_Pwr_Idle( Pwr_Err_Idle ) 28463 , .Sys_Pwr_WakeUp( Pwr_Err_WakeUp ) 28464 , .WrCxt( ErrWrCxt ) 28465 ); 28466 assign Req1_Urg = Req1_OpcT == 4'b1001; 28467 assign CxtEn = NextTrn & ReqHead & ~ ( Req1_Urg ); 28468 assign u_5717 = CxtEn & CxtId | ErrWrCxt; 28469 assign Req1_AddNttp = Req1_RawAddr & ~ { IdInfo_1_AddrMask , 2'b0 }; 28470 assign Req1_AddLd0 = Req1_AddNttp [7:0]; 28471 assign Rsp0_Vld = GenLcl_Rsp_Vld; 28472 assign Rsp1_Vld = Rsp0_Vld; 28473 assign Rsp_Rdy = RxPkt_Rdy; 28474 assign Rsp1_Rdy = Rsp_Rdy; 28475 assign NextRsp1 = Rsp1_Vld & Rsp1_Rdy; 28476 assign Req1_Addr4Be = Req1_Addr [1:0]; 28477 assign Cxt_0 = { u_3d2e , u_77fb , u_da22 , u_31e2 , u_bb4d , u_f3f5 , u_703a }; 28478 assign CxtPkt_AddLd0 = u_4e00 [18:11]; 28479 assign CxtPkt_Addr4Be = u_4e00 [9:8]; 28480 assign CxtPkt_Echo = u_4e00 [25:23]; 28481 assign CxtPkt_Head = u_4e00 [10]; 28482 assign CxtPkt_Len1 = u_4e00 [31:26]; 28483 assign CxtPkt_OpcT = u_4e00 [22:19]; 28484 assign CxtPkt_RouteIdZ = u_4e00 [7:0]; 28485 assign u_b46 = Cxt_0; 28486 assign CxtRsp1_Head = u_b46 [10]; 28487 assign Rsp1_Head = CxtRsp1_Head; 28488 assign Rsp_Head = Rsp1_Head; 28489 assign RxPkt_Head = Rsp_Head; 28490 assign Rsp0_Last = GenLcl_Rsp_Last; 28491 assign Rsp1_Last = Rsp0_Last; 28492 assign Rsp_Last = Rsp1_Last; 28493 assign RxPkt_Last = Rsp_Last; 28494 assign CxtRsp1_OpcT = u_b46 [22:19]; 28495 assign Rsp_OpcT = CxtRsp1_OpcT; 28496 assign RxPkt_Opc = Rsp_OpcT; 28497 assign CxtRsp1_Addr4Be = u_b46 [9:8]; 28498 assign CxtRsp1_Len1 = u_b46 [31:26]; 28499 assign Rsp_Be = 28500 RspBe 28501 & { 4 { ( CxtRsp1_OpcT == 4'b0000 | CxtRsp1_OpcT == 4'b0001 | CxtRsp1_OpcT == 4'b0010 | CxtRsp1_OpcT == 4'b0011 ) } }; 28502 assign Rsp0_Data = GenLcl_Rsp_Data; 28503 assign Rsp1_Data = Rsp0_Data; 28504 assign Rsp_Data = Rsp1_Data; 28505 assign Rsp_DataLast = Rsp_Last; 28506 assign Rsp0_Status = GenLcl_Rsp_Status; 28507 assign Rsp1_Status = Rsp0_Status; 28508 assign Rsp2_Status = Rsp1_Status; 28509 assign Rsp_DataErr = Rsp2_Status == 2'b01; 28510 assign RxPkt_Pld = Rsp_Pld; 28511 assign RxPkt_Status = Rsp_Status; 28512 assign Rsp_Vld = Rsp1_Vld; 28513 assign RxPkt_Vld = Rsp_Vld; 28514 assign uu_4e00_caseSel = { TxPktCxtId } ; 28515 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 28516 if ( ! Sys_Clk_RstN ) 28517 u_3d2e <= #1.0 ( 6'b0 ); 28518 else if ( u_5717 ) 28519 u_3d2e <= #1.0 ( ErrWrCxt ? ErrCxtWr_Len1 : Req1_Len1 ); -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Not Covered


27380 , .Sys_Clk_RstN( Sys_Clk_RstN ) -1- 27381 , .Sys_Clk_Tm( Sys_Clk_Tm ) ==> 27382 , .Sys_Pwr_Idle( ) -2- 27383 , .Sys_Pwr_WakeUp( ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27385 , .Tx_Head( RspTx_Head ) -1- 27386 , .Tx_Rdy( RspTx_Rdy ) ==> 27387 , .Tx_Tail( RspTx_Tail ) -2- 27388 , .Tx_Vld( RspTx_Vld ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27390 ); -1- 27391 assign CxtRdy = Rsp_Rdy; ==> 27392 rsnoc_z_H_R_U_P_Hs_654f724d_A0011420 Ip( -2- 27393 .Rx_2( u_8bb4_2 ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27395 , .Rx_4( u_8bb4_4 ) -1- 27396 , .RxRdy( RspRdy ) ==> 27397 , .RxVld( WrCxt ) -2- 27398 , .Sys_Clk( Sys_Clk ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


27414 assign u_6_WAIT_RSP = Empty & RspRdy; -1- 27415 rsnoc_z_T_C_S_C_L_R_Fsm_409a53b3 FsmCurState( ==> 27416 .Clk( Sys_Clk ) -2- 27417 , .Clk_ClkS( Sys_Clk_ClkS ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered

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